This application is a continuation of U.S. application Ser. No. 11/520,972, filed on Sep. 14, 2006, entitled “Power Supply Noise Rejection In PLL Or DLL Circuits,” the disclosure of which is incorporated herein by reference.
This application is directed to a phase-locked loop (PLL) or delay-locked loop (DLL) with high power supply noise rejection and low power operation.
A phase-locked loop (PLL) is a closed-loop feedback control system that generates an output signal and maintains that signal in a fixed phase relationship with a reference signal. A conventional PLL includes a phase detector, a loop filter and a voltage-controlled oscillator (VCO). The VCO generates a periodic output signal having a frequency that is dependent on a control signal. The VCO may initially be brought to the same frequency as the reference signal by means of a separate frequency detector or by means of a combined phase/frequency detector. After frequency lock has been obtained, the phase detector detects phase differences between the output signal and the reference signal and modifies the VCO control signal so as to adjust the output signal to be in a predetermined phase relationship with the reference signal.
A delay-locked loop (DLL) is similar to a PLL, with the VCO being replaced with a voltage-controlled delay line (VCDL). The VCDL receives an input signal and generates an output signal as a time-delayed version of the input signal, the delay of the output signal with respect to the input signal being a function of a control signal.
The VCO or VCDL is coupled to a power supply that supplies its operating current. However, power supply noise, that is, variations in the power supply voltage, may vary the phase of the output signal relative to the reference signal, introducing jitter into the output signal. Thus, it is desirable for the PLL or DLL to reject power supply noise.